1. Field of the Invention
The present invention relates to a clock recovery circuit of a demodulator.
2. Description of the Related Arts
FIG. 24 illustrates a conventional clock recovery circuit, as disclosed in "A Study on High Speed Clock Recovery Circuit for all digital demodulator--Block Clock Recovery Scheme--", The Institute of Electronics, Information and Communication Engineers of Japan, Technical Report SAT90-31, November 1990. In FIG. 24, Ich and Qch signals obtained by a quasi-coherent detection are input to A/D (analog-digital) converters 4 and 5 from input terminals 1 and 2, respectively. A clock oscillator 3 generates a fixed frequency clock of this receiver to the A/D converters 4 and 5 and the A/D converters 4 and 5 operate in synchronism with this fixed frequency clock to perform the A/D conversion. Two random access memories RAM1 6 and RAM2 7 store one slot length of digital Ich and Qch signals. The RAM1 6 and the RAM2 7 constitute a two-port RAM 100. In this two-port RAM 100, while the signals are stored in one off the RAM1 6 and the RAM2 7, the signals stored in the other of the same are processed.
A non-linear processor 8 inputs the digital Ich and Qch signals and produces a clock component from the received signals. A clock phase detector 9 inputs the output signal of the non-linear processor 8 and detects a phase of a symbol clock of the received signals. The non-linear processor 8 and the clock phase detector 9 constitute a clock phase estimator 101. An interpolator 10 calculates an interpolation from the output signals of the two-port RAM 100 and the clock phase estimator 101 and outputs decision point data and the interpolated Ich and Qch data are output from respective output terminals 11 and 12.
FIG. 25 shows a construction of the non-linear processor 8 shown in FIG. 24. In FIG. 25, the digital Ich and Qch signals are input to first and second square circuits 22 and 23 via input terminals 20 and 21, respectively, and the first and second square circuits 22 and 23 square the input signals. An adder 24 sums the output signals of the first and second square circuits 22 and 23 and outputs the sum of them from an output terminal 25.
FIG. 26 shows a construction of the clock phase detector 9 shown in FIG. 24. In FIG. 26, a phase generator 32 inputs the clock signal output from the clock oscillator 3 via a clock input terminal 31 and operates in synchronism with the clock signal to output phase information (0 to 2.pi. or -.pi. to .pi.) of a symbol clock cycle. A COS/SIN wave generator 33 outputs sine (SIN) and cosine (COS) values corresponding to the output values of the phase generator 32. The output signal of the non-linear processor 8 is fed to first and second multipliers 34 and 35 via an input terminal 30 and the cosine and sine values output from the COS/SIN wave generator 33 are also sent to the first and second multipliers 34 and 35. The first and second multipliers 34 and 35 multiply the respective input signals and output the multiplication results to first and second integrators 36 and 37, respectively. The first and second integrators 36 and 37 each integrate one slot length of the respective multiplication result values.
A phase calculator 38 calculates an estimated phase difference between the symbol clock included in the received signals and the output value of the phase generator 32 from the output signals of the first and second integrators 36 and 37 to output the estimated phase difference from an output terminal 39.
Next, the operation of the above-described conventional clock recovery circuit will now be described.
First, the Ich and Qch signals input via the input terminals 1 and 2 are converted into digital Ich and Qch signals in synchronism with the clock signal of the clock oscillator 3 of the receiver in the A/D converters 4 and 5. At this time, the oscillation frequency of the clock oscillator 3 is set to nearly N times the symbol rate. That is, with n times of oversampling, the A/D conversion of the signals is carried out.
The obtained digital Ich and Qch signals are separated into two, and are input to the two-port RAM 100 and to the non-linear processor 8. In the non-linear processor 8, the Ich and Qch signals are squared in the respective first and second square circuits 22 and 23 and the squared results are summed in the adder 24 to output the addition result P(n). This is expressed in formula (1) EQU P(n)={I(n)}.sup.2 ( 1)
(N=0, 1, 2 . . . )
wherein I(n) and Q(n) represent the A/D-converted Ich and Qch signals, respectively, at a sampling time n.
Next, the output signal P(n) of the non-linear processor 8 is fed to the first and second multipliers 34 and 35 which calculate the multiplication of the output signal P(n) by the respective cosine and sine values output from the COS/SIN wave generator 33 to output D.sub.c (n) and D.sub.s (n), respectively, as follows. EQU D.sub.c (n)=P(n).times.COS{.theta..sub.clk (n)} (2) EQU D.sub.s (n)=P(n).times.SIN{.theta..sub.clk (n)} (3)
(n=0, 1, 2 . . . )
In these formulas, EQU .theta..sub.clk (n)=2.pi./N.multidot.n (4)
(N=an oversampling number)
(n=0, 1, 2 . . . )
wherein .theta..sub.clk (n) is a modulus of 2.pi. and its obtainable value is 0.ltoreq..theta..sub.clk (n)&lt;2.pi..
Then, the first and second integrators 36 and 37 integrate one slot length of the outputs of the respective first and second multipliers 34 and 35 to output integrated values S.sub.c and S.sub.s as follows. ##EQU1##
L: a sample number within one slot
The phase calculator 38 inputs the S.sub.c and the S.sub.s and calculates an estimated phase difference .theta..sub.o (rad) between the symbol clock of the received signals and the output value of the phase generator 32 to output the calculation result to the output terminal 39. A calculation method of .theta..sub.o will be described as follows.
First, it is assumed that S.sub.comp is represented as a complex number as follows. EQU S.sub.comp =S.sub.c +jS.sub.s ( 7)
At this time, .theta..sub.o is expressed as follows. EQU .theta..sub.o =arg(S.sub.comp) (8)
(0.ltoreq..theta..sub.o &lt;2.pi.)
That is, in the phase calculator 38, after the received signals are squared, a Discrete Fourier Transform (DFT) of the squared values at the frequency of the symbol clock of the received signals is calculated to obtain the phase information of the clock component of the received signals.
Then, the interpolator 10 interpolates the signals stored in the two-port RAM 100 by using the estimated phase difference .theta..sub.o as the output signal of the clock phase estimator 101 and calculates a value at a decision point (in the case of a Nyquist waveform, a Nyquist point) to output this value. As one example of an interpolating calculation, a method using the first-order Lagrange's formula will be described.
First, the interpolator 10 calculates the position of the decision point of the signals stored in the two-port RAM 100 from the estimated phase difference .theta..sub.o. Now, it is assumed that .theta..sub.o is within the following formula EQU 2.pi./N.multidot.i.ltoreq..theta..sub.o &lt;2.pi./N.multidot.(i+1) (9)
but i is an integer within a range of 0.ltoreq.i.ltoreq.(N-1).
At this time, the a phase .theta..sub.D (n) at the decision point of the m-th symbol of the data stored in the two-port RAM 100 exists in a range represented in the following formula. In this case, L is the sample number within one slot. EQU N.multidot.m+i.ltoreq..theta..sub.D (n).ltoreq.N.multidot.m+(i+1) (10)
(m=0, 1, 2 . . . ) EQU N.multidot.m+(i+1).ltoreq.L-1
Next, in the interpolator 10, in order to calculate the respective Ich and Qch decision point data I(m) and Q(m) of the m-th symbol by using the interpolation, the Ich and Qch data with subscript are read out of the two-port RAM 100 as follows. EQU I.sup.- (m)=I(N.multidot.m+i) EQU I.sup.+ (m)=I(N.multidot.m+i+1) EQU Q.sup.- (m)=Q(N.multidot.m+i) EQU Q.sup.+ (m)=Q(N.multidot.m+i+1) (11)
By using the following formula, the decision point data I(m) and Q(m) are calculated and output.
FIG. 27 illustrates a principle of an interpolation process relating to Ich. As is apparent from FIG. 27, the following formula can be derived. EQU I(m)={a.multidot.I.sup.- (m)+b.multidot.I.sup.+ (m)}/(a+b) EQU Q(m)={a.multidot.Q.sup.- (m)+b.multidot.Q.sup.+ (m)}/(a+b) (12)
wherein a=2.pi./N.multidot.(i+1)-.theta..sub.o and b=.theta..sub.o -2.pi./N.multidot.i.
The interpolator 10 calculates one slot of data as described above and outputs the decision point data I(m) and Q(m) from the respective output terminals 11 and 12. At this time, the number of the data taken out of the two-port RAM 100 for the interpolation is different depending on an interpolation system applied and, for example, in the case of the second-order Lagrange's formula, three points near the decision point can be used.
As described above, although a case of the first-order Lagrange's formula has been described, a case of the second-order Lagrange's formula is also similarly described in the aforementioned document.
In the conventional clock recovery circuit, as shown in FIG. 24 to FIG. 27, the recovered clock can be produced based on the estimated phase difference between the output value of the phase generator and the symbol clock of the received signals. Hence, the period of the recovered clock becomes the period of the output signal of the phase generator operating in synchronism with the fixed frequency clock. In other words, in the conventional clock recovery circuit, of the recovered clock, only the phase difference from the output value of the phase generator is corrected but the frequency difference can not be controlled.
Therefore, in case of communication using a burst mode in which the estimated phase difference between the symbol clock of the received signals and the output value of the phase generator is hardly varied during a so-called burst, no problem arises, but in the case of a continuous mode transmission, this estimated phase difference can not be ignored. As a result, a slip of the recovered clock will occur.